This entry is part 2 of 10 in the series PCB Design

Once the design is ready it is needed to be verified by the designer itself before submitting it for review. We have categorized the checklist in multiple sections for a systematic checking. There are many details that go into making a successful first – run design, and this checklist helps prevent bugs from marrying a healthy design otherwise. This list is taking inspiration from AQDI.COM and adds furthermore design checks to it. We have tried to be as elaborate as possible, yet engineers are encouraged to add more checkpoints for better results. The idea is for engineers and technicians to share experiences and create a detailed checklist that can be tailored to meet their specific needs by the individual designer.

Design related checklist

  • Check with the high-level documentation if all the requirements are translated into design properly or not. [1]
  • In most cases, 90% of design is based on some reference design or previous design make sure all essence of the original design is captured properly. [2]
  • Make sure the remaining 10% of the schematic is properly simulated or logically evaluated for proper functionality. [3]
  • Race conditions are checked. [4]
  • Each IC has a predictable or controlled power-up state. [5]
  • Check the datasheet fine print and app notes for weird IC behaviours.[6]
  • Amplifiers checked for stability.[7]
  • Oscillators checked for reliable startup.[8]
  • Pull-ups on all open collector / open drain outputs.[9]
  • Reset circuit design reliability checked, for both glitch-free and consistent operation.[10]
  • Check time delays and slew rates of opamps used as comparators.[11]
  • Check opamp input over-drive response for unintended output inversion.[12]
  • Check common mode input voltages on opamps.[13]
  • Voltage ratings of components checked.[14]
  • Output driver current checked.[15]
  • Setup, hold and access times for data and address buses validated.[16]
  • Use of baud rate friendly clock source for devices that have serial ports.[17]
  • Mating connectors on different assemblies checked for the same pinout.[18]
  • Off-board connectors identification for all signals, even if not used on this design.[19]
  • Card edge connectors identification for the mating parts.[20]
  • Ground made first and breaks last for hot pluggability in the connector.[21]
  • Calculate current consumption properly for selection of PMIC/LDO.[22]
  • Verify if every signal has a proper return path available. There should be no break in ground signal.[23]

General checklist

  • All unused inputs terminated.[24]
  • For buses, ensure bus order matches device order.[25]
  • All no-connect pins on IC’s should be labelled NC.[26]
  • Unpopulated parts annotated and enclosed by the dashed-line box on schematics.[27]
  • Wires exist between all connected pins/ports (no direct pin/pin connections).[28]
  • Avoid direct connect of mode pins or no-connect bus lines to GND or VCC so PCB reworks options are maximal (add 0-ohm resistor).[29]
  • Connect DIP switches and other grouped I/O to ports in a logical way, i.e. LS bit to LS bit and MS bit to MS bit.[30]
  • Polarized components checked for connected polarity.[31]
  • Check pin numbers and pin type assignment of all custom-generated parts.[32]
  • Check if no dot is present on any pin after ERC run.[33]
  • Check for single nets.[34]
  • Check for multi-driven nets.[35]
  • Check all the specific instructions are noted down near each component/net that can be utilized in layout e.g. High-frequency net, matched impedance net value, thermal requirement etc.[36]
  • Mechanical artefacts e.g. a screw, heatsink etc. should be added in schematic and it should be decided if they are connected to any net or isolated.[37]

Bill of material(BoM) related checklist

  • Each component has quantity, reference designator and description.[38]
  • Suggested and alternate manufacturer(s) listed.[39]
  • Price and availability checked for each component.[40]
  • Part is verified against schematic value and assigned footprint.[41]

Power Integrity related checklist

  • Adequate bypass cap for each IC.[42]
  • Electrolytic and tantalum capacitors checked for no reverse voltage.[43]
  • Check hidden power and ground connections.[44]
  • Sufficient power rails for analog circuits.[45]
  • Sufficient capacitance on low dropout voltage regulators.[46]
  • High PSRR regulator selection for sensitive and high-speed circuitry.[47]
  • No power or ground loop exists.[48]
  • No hidden ground connection between isolated sections.[49]
  • Check for the ferrite bead/resistor current carrying capacity used in power line.[50]
  • Ensure that MLCC used are having at least twice the voltage rating than required.[51]
  • Ensure Tantalum/Electrolytic capacitors used are having at least 1.5 times rated voltage than required.[52]
  • Ensure that high-frequency high power devices powered by a separate regulator with(/or) adequate filtering.[53]

Electro-magnetic compatibility related checklist

  • All outside world I/O lines filtered for RFI.[54]
  • All outside world I/O lines protected against static discharge.[55]
  • Consider signal rate-of-rise and fall for noise radiation.[56]
  • Separate analog signals from noisy or digital signals.[57]
  • Under-utilization of gates on multi-gate parts checked.[58]
  • Clock lines with series termination and parallel termination component locations present even if not populated.[59]
  • Piezo elements generate voltages (when shocked) that can destroy their drivers — check for susceptibility.[60]
  • Isolation is not always necessary for design, use engineering judgement to decide. Magnetic isolation increases susceptibility.[61]

Reliability related checklist

  • Check for input voltages applied with power off and CMOS latch-up possibilities.[62]
  • Check maximum power dissipation at worst-case operating temperatures. find if heat-sink is required.[63]
  • Determine the effect of losing each of multiple grounds on a connector.[64]
  • Automotive powered devices must withstand 60 to 100-volt surges.[65]
  • Check for voltage transients and high voltages on FET gates.[66]
  • Estimate the total worst case power supply current.[67]
  • Ensure resistors are operating within their specified power range plus a safety factor.[68]
  • Check for low impedance sources driving tantalum caps which can cause premature failure.[69]
  • Avoid reverse base-emitter current/voltage on bipolar transistors.[70]

Test ability checklist

  • Ability to disable watchdog timer for testing, diagnostics and emulation.[71]
  • Ability to isolate/ off the power supply for a certain section of design to test.[72]
  • Diagnostic resources by design (LEDs, serial ports, etc.) even if unpopulated by default.[73]
  • Test points on power and ground lines.[74]

Life-cycle checklist

  • Part obsolescence review.[75]
  • Replacement part compatibility with software requirements.[76]

Aesthetics and traceblity related checklist

  • The filename on each sheet.[77]
  • A minimum number of characters in values.[78]
  • Consistent character size for readability.[79]
  • Schematics printed at a readable scale.[80]
  • All components have reference designators and values.[81]
  • Special PCB or parts list information entered for each component if required.[82]
  • Power and ground pins listed for each component.[83]
  • Title block completed for each sheet.[84]
  • Revision history noted for all changes on the front page.[85]
  • Block diagram is available and consistent with the schematic in block characteristics and signals flow.[86]
  • Schematic should also contain logos that are supposed to be printed on PCB.[87]
  • Text should not overlap wire or symbol graphics on schematics.[88]
  • Busses with off-page destinations present with a title at page margin.[89]
  • Page title present and consistent on all pages if not in the title block.[90]
  • Symbols identify open collector/drain pins and internal pull up/down pins.[91]
  • Pin names and attributes on symbols with multi-function pins should match actual design usage (I/O/Bi, Name).[92]
  • Preferred component reference designators.[93]
    • R: fixed resistor
    • RN: resistor network
    • RV: variable resistor
    • C: capacitor
    • CN: capacitor network
    • CV: variable capacitor
    • L: inductor
    • Q: transistor, FET, SCR, TRIAC
    • D: diode, rectifier, Zener, LED
    • DL: multisegment display (any type)
    • VR/U: voltage regulator
    • U: integrated circuit
    • J: socket, jack (female)
    • P: plug (male)
    • JP jumper (pins, trace, or wire)
    • Y/X: crystal
    • M: modular subassembly, daughter board
    • S: mechanical switch
    • F: fuse
    • FB: ferrite bead
    • FL: filter
    • T: transformer
    • KB: keyboard
    • BT: battery

MTBF

  • Check failure modes and effects of failed power semiconductors.[94]
  • Electrolytic/tantalum capacitor temperature/voltage derating sufficient for MTBF.[95]
  • Resistor power ratings derated for elevated ambient temperatures.[96]
  • Components which are picked need to have the required margins.[97]
  • Check if the number of components can be reduced to achieve the same functionality and reliability.[98]
  • Calculate the mean-time between failure (MTBF) of the complete design using MTBF of individual components provided by the manufacturer.[99]

Environmental checklist

  • RoHS compliance requirement review.[100]

By Purnendu Kumar

Purnendu is currently working as Senior Project Engineer at QuNu Labs, Indias only Quantum security company. He has submitted his thesis for Masters (MS by research 2014-17) in electrical engineering at IIT Madras for doing his research on “constant fraction discriminator” and “amplitude and rise-time compensated discriminator” for precise time stamping of Resistive Plate Chamber detector signals. In collaboration with India Based Neutrino observatory project, he has participated in design and upgrade of FPGA-based data acquisition system, test-jig development, and discrete front-end design. After completion of his bachelors in Electrical Engineering (Power and Electronics), he was awarded Junior Research Fellowship at Department of Physics and Astro-physics, University of Delhi under same (INO) project. His current interest is in high-speed circuit design, embedded systems, IoT, FPGA implementation and optimization of complex algorithms, experimental high-energy physics, and quantum mechanics.