This entry is part 8 of 10 in the series PCB Design

A good list of checks to make before committing the design of a new printed circuit board is an essential ingredient for quality assurance. We are presenting here an extended checklist for the designer as well as a reviewer.

There are two kinds of designers, those who are designing antennas on purpose and those who aren’t.

Eric Bogatain

Preliminary checks

Schematic review completed, including pin swaps done during layout.
Layout DRC is run in the tool and it is found 100% clean.

Footprint checks

Verify schematic symbol matches the selected package.
Confirm pinout diagram is from the top or bottom of the package.
Print PCB on paper with a 1:1 ratio and match with physical parts.
Obtain the 3D model and check against footprints.
Soldermask apertures on all SMT lands and PTH pads.
SMD pad shapes checked
Thermal reliefs for internal power layers.
It’s better to create a do-not place/do-not route area with every part of footprint design. In this way, the DRC tool will easily catch any interference between the parts.
No uncapped vias in pads. (except low-power QFNs where some voiding is acceptable)
QFN paste prints segmented.
Solder paste small pads 100% size, larger pads reduced to avoid excessive solder volume.
Adequate clearance around pads (typically 50 um).
Solder mask does or does not cover vias.
Solder mask swell checked.

Part placement

Check if part orientation is consistent.
Components >=0.2″ from edge of PCB.
Appropriate clearance is provided between the parts.
Check the direction of all polarized components.
Every IC has bypass capacitors near the power pin placed near to the body. (A direct connection, without via is preferable but in some cases(e.g. BGA components) it is not possible.)
Verify all series termination is located near source.
Verify all parallel termination is located near the sink.
I/O drivers are placed near connectors.
RFI/EMI filtering is provided as close as possible to entry/exit of the board.
Placement should be in such a way that during repair any IC should not be removed to replace others.
SMD component orientation arbitrary or consistent.
Ensure pin 1 interpretation and orientation consistent among all connectors of a given type on the board.
Preferably put all wired connectors including power input to one side of the board. (There should be no high-speed circuit between two wired connectors, else they tend to make unwanted antenna easily.)

Routing check


Provide multiple vias for high current and/or low impedance traces.
Sufficient width for planes/traces for required current.
Sufficient clearance for high voltage traces.
Minimal slots in planes from via anti-pads.
Check all power and ground connections to ICs.
Check for power not shorted to ground.


No vias/trace under metal-film resistors and similar poorly insulated parts.
Check for dead-end traces, unless used on purpose.
Check crystal connections are short.
High-frequency crystal cases should be flush to the PCB and grounded.
Check for traces running under noisy or sensitive components.
Digital and analog signal commons joined at only one point.
Routing should be away from PCB edge inside the ground boundary.
Automated and manual netlist check.
Trace and space geometry noted.
No sharp turns in traces.
No acute angles in planes.
Check if there are any Isolated copper nets.
Blind and buried vias allowed on multilayer PCB.

Sensitive analog

Guard ring / EMI cages provided if needed.
Physically separated from high current SMPS or other noise sources.
MLCC can act as a sound sensor in the presence of loud audio source.


Ensure that all high-speed signal traces run over their own ground/power planes. Do not allow a digital signal to travel over the analog plane unless it goes to a device in that area and then follows the digital ground trace devices to minimize the loop and therefore noise.
If there are any slots or gaps in the Ground/Power plane, no high-speed signals should run over them.
Sufficient clearance to potential aggressors to minimize the cross-talk.
Check length matching if required.
Trace width checked for controlled impedance.
Check pad width on connectors and add plane cutouts if needed to minimize impedance discontinuities.
For high-speed signals minimise track stubs (to below the critical length – ideally < 6.5mm, no more than 12mm for a 1ns rise time signal).
Ideally, high-speed connectors should have the ground plane getting through between pins to avoid signal return paths having to go round the connector to a ground pin on it.

Differential Pair

Differential pair tracks are spaced based on impedance calculation?
Skew is matched?
Clearance from non-coupled nets provided?

Mechanical check

LEDs, buttons, and other UI elements on the outward-facing side of the board.
Stress-sensitive components (MLCC) oriented to reduce the effect of stress.
Clearance around large ICs for heatsinks/fans if required.
Clearance around pluggable connectors for mating cable/connector.
Clearance around mounting holes for screws.
Plane keep-outs and clearance provided for shielded connectors, magnetics, etc.
Confirm PCB dimensions and mounting hole size/placement against enclosure or card rack design.
Verify the mounting hole connection/isolation.
Hole diameter on the drawing is finished sizes, after plating.
Components not physically overlapping/colliding.
Clearance provided around solder-in test points for probe tips.
Finished hole sizes are >=10 mils larger than lead.
All tolerance noted with reasonable approximation.
Pads >=15 mils larger than finished hole sizes.
Test pads 200 mils from the edge of the board (unless required by design).
If the circuit board is going into a tight-fitting enclosure, have component heights and other mechanical keep-outs been accounted for?
Does the fabrication drawing show the PCB outer dimensions?
Mounting holes electrically isolated or not.
Mounting holes with or without islands.
Proper mounting hole clearance for hardware.
Mounting holes matched 1:1 with mating parts.
Drill legend shows all symbols and sizes.
Check plots sent with disk-based photo plot files.
NC drill and photo plot file language format noted.
Tools on drill plot and NC drill file cross-checked.
Solder mask over bare copper noted if needed.
PCB thickness, material, copper weight noted.
Printed drill report sent with check plots.
Printed aperture table sent with check plots.
Photoplot files checked in the file viewer.
Test coupon on PCB containing minimum geometry features.

Thermal check

Solid connections used to planes if heatsinking.
Ensure thermal balance on components of SMT chips to minimize the risk of stoning.
Do high power components have adequate heat sinking using PCB copper heatsink or mechanical heat sink? (check data-sheet of thermal requirements. In case of FPGA perform power estimation using tool provided).
Standoffs on power resistors or other hot components.

Silkscreen check

Silkscreen legend text weight >=10 mils.
No silkscreen legend text over vias (if vias are not solder masked) or holes.
All legend text reads in one or two directions.
Components labelled left-right, top-bottom.
Company logo in silkscreen legend.
Company logo in foil.
The copyright notice on PCB.
Date code on PCB.
PCB part number.
PCB revision on silkscreen legend.
Assembly revision blank on silkscreen legend.
Serial number blank on silkscreen legend.
All silkscreen text located to be readable when the board is populated.
All ICs have pin one clearly marked, visible even when the chip is installed.
High pin count ICs and connectors have corner pins numbered for ease of location.
Silkscreen tick marks for every 5th or 10th pin on high pin count ICs and connectors.
Coupons for board part number, anti-static warning, QC markings.
PCB has ground turrets, power rail test points, and test points for important signals, all labelled.

Design for Testing(DFT)

Test pad or test via on every net to allow in-circuit test.
Provide ground test points, accessible and sized for scope ground clip.
Does the board include adequate structures or connectors for firmware load or functional test?
If the board is intended for high volume manufacturing, does the design include bottom side solder mask openings to allow for a bed of nails in-circuit test?

Design for Manufacturing(DFM)


All design rules within the manufacturer’s capability.
Minimize the use of vias/traces that push fab limits.
Controlled impedance specified in fab notes if applicable.
Stackup verified with the manufacturer and specified in fab notes.
Board finish specified in fab notes.
If penalizing, add panel location indicators for identifying location-specific reflow issues.
Layer number markers specified to ensure correct assembly.
Panelized PCB fits test and manufacturing equipment.
Board outline indicated on the fabrication drawing and solder mask top (SMT) layer.
Export Gerber/drill files at the same time to ensure consistency.
Visually verify final CAM files to ensure no obvious misalignments.


Visual references for automated assembly.
Tooling holes for automated assembly.
Are surface mount components used wherever possible instead of through holes? This improves assembly automation, quality, and manufacturing cost.
For all through-hole components, are the bottom side copper rings nice and wide (copper diameter >= drill diameter + 40 mils) to allow for easy wave/hand soldering? Pins that are tight pitch can use ovals or rectangular annular rings?
Are bottom side SMT components appropriately spaced (> 250 mils) away from through-hole pins?
Do all traces and components have sufficient clearance (>30 mils) away from the edge of the board?

By Purnendu Kumar

Purnendu is currently working as Senior Project Engineer at QuNu Labs, Indias only Quantum security company. He has submitted his thesis for Masters (MS by research 2014-17) in electrical engineering at IIT Madras for doing his research on “constant fraction discriminator” and “amplitude and rise-time compensated discriminator” for precise time stamping of Resistive Plate Chamber detector signals. In collaboration with India Based Neutrino observatory project, he has participated in design and upgrade of FPGA-based data acquisition system, test-jig development, and discrete front-end design. After completion of his bachelors in Electrical Engineering (Power and Electronics), he was awarded Junior Research Fellowship at Department of Physics and Astro-physics, University of Delhi under same (INO) project. His current interest is in high-speed circuit design, embedded systems, IoT, FPGA implementation and optimization of complex algorithms, experimental high-energy physics, and quantum mechanics.