This entry is part 1 of 10 in the series PCB Design

Creating a large design from a given feature set and assuring its success in the very first iteration could be challenging if proper attention is not given to reviewing it strictly. This article is going to cover the review part of the schematic design in a hardware flow which ensures minimum error and hence maximum reliability. Sometime it may feel as to review is a waste of time, especially when the deadline is approaching. But believe me its the key to ultimate success. The time spent here saves the time spent in finding the bug, and the re-iteration time. Money saved along the path is another benefit to consider. A review can save time as well as money if performed with criticality and precision. The situation may arrive that same person is designer as well as a reviewer, in such cases person has to completely disconnect from self-confidence over his/her design and try to find issues. Although as long as possible we should try to avoid this situation and hence review can be independent of designers perspective. A good reviewer should also be the subject expert or it might be recommended to get different parts of design reviewed by respective experts. If multiple people are involved in review one more review is recommended by team leaders to look at the complete design in one big picture. As per my opinion, the review should not be a single task, rather it should be broken in multiple steps and after each step information should be passed to designer and review should resume after updates. The main purpose to divide this into multiple steps is to reduce the error to such a small extent that first iteration design success can be guaranteed. From intuition, it might seem that step 3-5 is already being performed in step 6 hence they might be skipped, but doing so will increase the time to review as multiple verifications per net have to be done while looking at multiple sources all-together. This also increases the chances of an error being overseen. We want to perform step 6 as final verification before approval and want minimum errors/warnings to be reported in this step. In some sense, step 1-5 completes the review process up to 95% and the last step is for leftover 5%.

Step:1 Understanding the requirements and the block diagram

  1. Get the required features document from appropriate source.
  2. Understand the block diagram, and look if they are properly translating to required feature set. In case any feature is not implemented contact to designer for clarification update and restart from Step 1.
  3. Get familier with the signal flow directions across blocks.
  4. Note down the block, major(active) components in block and related pagenembers.
  5. Check for the race condition at block level.

Step 2. Collecting the required data set

  1. Generate/Receive(If provided by designer) BOM for the given schematic and verify if the value, description and footprint name matches in the BOM.
  2. Make sure all datasheet for all components in BOM is available with you beforehand, else download them.
  3. Make sure that best device is chosen for given operating condition(high efficiency, small footprint or low cost).
TR4 Stratix IV Power Tree

Step 3. Power supply verification

  1. Ask for the power tree from the designer, or create one based on the given schematic to understand the power flow. Power tree should contain the information regarding voltage at each node, which block/components it is supplying, and which ground reference is used(if the design has multiple grounds).
  2. Update the Power tree with interconnect between grounds. Make sure that the ground return path is available everywhere.
  3. Ask for current calculation sheet from the designer, or create one. To create such a sheet, all datasheet of components used in the schematic should be handy. Update the power tree with current in each branch.
  4. Verify the power supply is correct for every component and the components in the power supply path (e.g. resistor/inductor) are capable of current carrying capacity mentioned in power tree. If any irregularity is found, report to the designer for clarification and update and restart from step 3 if no components are changed, else start from step 2.
  5. Check if necessary filter is provided at power inlet so that it should not polute the power supply itself. Inform the Designer.

Step 4. Active Component wise verification

  1. Match the pinout of Schematic symbol with the datasheet. Check if Thermal PAD is also given a pin or not. If any irregularity is found, report to the designer for clarification and update and restart from step 4.
  2. Generally, each component datasheet contains the optimum value of peripheral components and a recomended design pattern, match this against the provided schematic with considerable design tolarance. If any irregularity is found. report to designer for clarification and update and restart from step 4 if no components are changed, else start from step 2.

Step 5. Isolation Verification

  1. If the design uses Isolated parts make sure to note them down separately.
  2. Make sure “no signal” even Ground is passing from one isolated block to another without Isolation(Capacitive/Magnetic/Optics). If any irregularity is found, report to designer for clarification and update and restart from step 5 if no components are changed, else start from step 2.

Step 6. Net-list Verification

  1. Generate/Receive netlist in following format : Sr.No., NetName, Level(Power,Analog,LVCMOS3.3,TTL. etc.), Frequency, Components with pin(e.g. U1.1 means component referenceU1 pin 1). Also, keep a PDF or print of schematic ready.
  2. Pick each net and verify if their connection is okay, in terms of voltage level, power handling capacity of the component connected to it and if it is not mistakenly connected to an unwanted component. Create a report and if a mismatch is found add as an error.
  3. Check for single nets. Add to report as Warning.
  4. Check for termination is the net is a high-speed signal. Add to report as an error.
  5. Check for un-necessary branching in any net if the speed of net is greater than 9KHz. All such branches should be either too small (<1 inch) or one on one connection should be made. Add to report as a warning.
  6. Check for the race condition on the net level. If violations are there Add to report as an error.
  7. With every node being checked, keep marking on the PDF/Printed sheet. Once all net are checked, find if there are any unmarked node left in schematic and report them as error/warning/no error based on engineering judgement.
  8. Share the report with designer and verify the corrections w.r.t the shared report before approving it for final approval.

After approval design is ready to be given to layout engineer along with the netlist generated in step 6 which will be used in layout decisions as well as layout verification.

By Purnendu Kumar

Purnendu is currently working as Senior Project Engineer at QuNu Labs, Indias only Quantum security company. He has submitted his thesis for Masters (MS by research 2014-17) in electrical engineering at IIT Madras for doing his research on “constant fraction discriminator” and “amplitude and rise-time compensated discriminator” for precise time stamping of Resistive Plate Chamber detector signals. In collaboration with India Based Neutrino observatory project, he has participated in design and upgrade of FPGA-based data acquisition system, test-jig development, and discrete front-end design. After completion of his bachelors in Electrical Engineering (Power and Electronics), he was awarded Junior Research Fellowship at Department of Physics and Astro-physics, University of Delhi under same (INO) project. His current interest is in high-speed circuit design, embedded systems, IoT, FPGA implementation and optimization of complex algorithms, experimental high-energy physics, and quantum mechanics.