This entry is part 7 of 10 in the series PCB Design

Following the finalization of the schematic and BOM of a design, the layout phase takes off. While the layout takes a considerable amount of time to do correctly, this is often the point where the schedule is compressed and rushed. While some portions of the circuit performance are dictated by the schematic and BOM, the PCB layout finally decide the fate of design. During layout, we often need to use engineering judgment on the trade-off between the size, cost, testability, and manufacturability of the board. Also now the design becomes more of a multi-disciplinary, e.g. thermal issues have to be kept in mind, material decides the electrical property of traces etc. A good reviewer of the PCB layout should be familiar with the type of circuit they are reviewing. In the PCB layout process, budget & time should be allocated to review the layout, make the necessary changes and then re-examine the new layout. The time you spend now can save frustration hours, days, and weeks later. A PCB layout review often saves a future PCB spin, which is a huge time and cost sink for any project.

Step 1: Data-collection preliminary verification

  1. Before starting the review make sure all the datasheet, reference designs and stack up details are available.
  2. Schematic design is verified and sign off is done.
  3. Layout DRC is run and its 100% clean.
  4. Verify the footprint of each custom component from the datasheet.
  5. Create the mind map of every schematic block related to the PCB section. This will help in finding parts letter for review.
  6. Ensure that mechanically board dimension is correct, and mounting holes are at correct positions with certain allowable tolerance.
  7. Check if any signal is running to the board edge.

Step 2: Placement

  1. Ensure decoupling capacitors are placed as close as possible to the pins.
  2. RFI and EMC filtering are placed as close as possible to entry/exit.
  3. Enough space is provided for rework, and heatsink mounting.
  4. Ensure if placement guideline of individual ICs is followed properly.
  5. Thinking in terms of current return part, analyze if analog and digital circuits are not mixed up. This will give rise to signal integrity issues.
  6. All wired connector is placed on one side of the board, to keep ground potential as close as possible. If there exists any potential, it will make an efficient antenna.
  7. Placement is done in such a way that trace length and cross-over are minimized.

Step 3: Routing

  1. Ensure commons of digital and analog circuit are joined at only one place.
  2. Every signal has its reference ground plane below it.
  3. The width of power planes should be proportionate to current it is carrying.
  4. Ensure there are minimum possible slottings in Power plane and ground plane should be continuous.
  5. Any plane should not create a loop with an empty area in mid.
  6. Ensure planes are removed below magnetics and filters, they are known to pollute the power.
  1. Check for dead-end traces unless designed on purpose.
  2. As much as possible ensure there are no traces below SMD components.
  3. Sensitive analog signals are provided guard rings.
  4. All traces are 20 mils inside the PCB edge.
  5. High-speed signals are not crossing breaks in the reference plane.
  6. Impedance matched signals are checked against the stack up detail provided by the manufacturer.

Step 4: Silk-screen

  1. No silkscreen on the pad or under IC.
  2. Common orientation is observed in design.
  3. Logo and revision number are mentioned on board.

PCB design has no certain rules and many rules contradict each other. As there is no fixed solution to one problem, it is sometimes considered as art, and here experience matters more than anything else.

By Purnendu Kumar

Purnendu is currently working as Senior Project Engineer at QuNu Labs, Indias only Quantum security company. He has submitted his thesis for Masters (MS by research 2014-17) in electrical engineering at IIT Madras for doing his research on “constant fraction discriminator” and “amplitude and rise-time compensated discriminator” for precise time stamping of Resistive Plate Chamber detector signals. In collaboration with India Based Neutrino observatory project, he has participated in design and upgrade of FPGA-based data acquisition system, test-jig development, and discrete front-end design. After completion of his bachelors in Electrical Engineering (Power and Electronics), he was awarded Junior Research Fellowship at Department of Physics and Astro-physics, University of Delhi under same (INO) project. His current interest is in high-speed circuit design, embedded systems, IoT, FPGA implementation and optimization of complex algorithms, experimental high-energy physics, and quantum mechanics.

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