Every designer generally employs a set of PCB layout guidelines while using their engineering judgement. These Guidelines set out best practice to reduce the cost of boards and to minimize the risk of errors arising during manufacture. A printed circuit board (PCB) mechanically supports and electrically connects electronic components using conductive tracks, pads and other features etched from copper sheets laminated onto a non-conductive substrate. PCBs can be single sided (one copper layer), double-sided (two copper layers) or multi-layer (outer and inner layers). Multi-layer PCBs allow for much higher component density. Conductors on different layers are connected with plated-through holes called via’s. Advanced PCBs may contain components – capacitors, resistors or active devices – embedded in the substrate. While during schematic design we mostly care about voltage level and current consumption, but here it becomes more important to think in terms of the current return path. The whole design process revolves on eliminating,
- Source of noise, if it is in the board
- Medium for noise to travel to sensitive components of design
- Sensitivity of the components towards noise
to achieve electromagnetic compatibility compliance. PCB design consists of mainly stack-up, component placement, and routing. Basic thumb-rules of these subparts will be the topic of another article. We will keep this article more abstract and focus on guidelines to achieve EMI EMC criteria.
The ability of an equipment or system to function satisfactorily in its electromagnetic environment without introducing intolerable electromagnetic disturbances to anything in that environment.
IEC 60050-161
High-speed signal
1. Minimize the length of the high-speed digital signal carrying paths.
High-speed digital signal and clocks are the strongest noise source. Longer the trace on board higher is the probability of these to couple into other parts making system noisy. This can be tricky sometimes, but with few permutation-combination, an optimal component placement can be achieved for optimal trace length.
2. Ensure continuous ground return-path below high-speed signals.
It is very evident that current always travels in the loop, and also generates the magnetic field whose strength is directly proportional to the loop area. An immediate return ground plane below high-speed signal provides a low impedance path and return current exactly follow the trace minimizing the loop area to lowest possible.
3. Do not route high-speed signals below components handling I/O’s.
Energy can couple easily to component inductively(magnetically) or capacitively(electrically) adding noise. This will drive common mode voltage between connectors making an effective antenna. Extending the same analogy, it is better to avoid using planes below filters used in the power line, as they possess the capability to pollute the signal in the plane/trace beneath them.
4. Bury the high-speed/critical signals inside.
Routing these signals in a plane, where they are sand-witched between two solid planes allow containing the field and hence avoid coupling. If it is required to route in exposed layers (Top/Bottom) it is always beneficial to use co-planer waveguide structure over micro-strip.
5. Characteristic impedance of trace should be properly matched at desired operating frequency.
electronics, impedance matching is the practice of designing the input impedance of an electrical load or the output impedance of its corresponding signal source to maximize the power transfer or minimize signal reflection from the load. In the case of a complex source impedance and load impedance, maximum power transfer is obtained when the source impedance equals the complex conjugate of the load impedance. When looking from the start of transmission line towards signal source we can say that the trace is acting as load hence its characteristic impedance should also be the same as the source. The impedance of trace can be controlled by controlling the width of trace and separation from the ground return plane. These values should be fixed during the stack-up decision.
6. High-speed (or susceptible) traces should be routed at least 20H from the board edge, where H is the distance between the trace and its return current path.
The electric and magnetic field lines associated with traces very near the edge of a board are not well contained. This PCB layout guideline minimizes the crosstalk and coupling between antennas and traces.
7. Differential pairs should be balanced.
Differential signals are less susceptible to noise and generate negligible radiated emissions if they are having the same length and maintain the same impedance relative to other conductors.
Power and ground
8. In a board with power and ground plane, no traces should be used to connect to power or ground.
Traces take up space and add inductance to the connection. If high – frequency impedance is a problem (as with power bus decoupling), it can significantly degrade the performance. Best practice will be to directly connect to plane using Vias.
9. A solid ground plane is a must.
It is advised to have no slots or gaps in the ground plane and a complete layer should be allotted to it. Also, make sure this plane is the return path for all high-speed (above 9 kHz) signals. As we know current takes the lowest impedance path, and hence for DC the current flow through the whole connector. This will intersect the current path of other high-speed signals creating signal integrity issues. Multiple ground plane can reduce the effect of this current flow.
10. All power and ground signals should be bounded to good antenna part at high frequency.
Unintended voltages between various conductors are a primary source of radiated emission and susceptibility issues. If multiple ground planes are used then any connection to ground at a given position should be made to all of the ground layers at that position. The main guiding principle here is that high-frequency currents will take the lowest inductance path if allowed to. The designer should not try to direct the flow of current.
11. Multiple power plane with same ground return should be placed in same layer.
For example, a board employs three voltages with the same power reference, then it is generally desirable to minimize the high-frequency coupling between these planes. Putting the voltage planes on the same layer will ensure that there is no overlap. Also, if two planes get too close to each other on the same layer, the significant high-frequency coupling may occur. keeping a minimum of 3 mm gap between planes is an optimum case.
12. Analog and digital return paths should be connected to one place.
Analog signals are more prone to noise with substantial degradation in SNR. It is better to keep a star grounding to avoid DC/any other current from digital part of circuit flowing through analog reference plane.
Considerations for antenna
13. The lengths of I/O traces should be minimized.
Traces attached directly to connectors are likely paths for energy to be coupled on or off the board. it is a best practice to place Filters/IO controller IC’s near to connector.
14. All connectors should be located on one edge or on one corner of a board.
Connectors are the most efficient antenna parts in the design. Placing them on the same edge of the board makes it much easier to control the common-mode voltage that may drive one connector relative to another. Also, all off-board communication from a single device should be routed through the same connector. As many components generate a significant amount of common-mode noise between different I/O pins.
Component selection
15. Select active digital components that have maximum acceptable transition times.
The power in the upper harmonics can be much higher than necessary if the transition times of a digital waveform are faster. These are the unwanted noise on PCB. It is wiser to decide on limits than reaching out for the fastest possible device.
PCB layout guidelines for EMC- Summary
There may be dozens, hundreds or even thousands of circuits in a typical circuit board. Each circuit is a potential energy source that could eventually be unintentionally linked to other circuits or devices. As a design engineer, it is more important to identify, isolate and suppress the adverse effects to achieve the EMC goals. PCB layout guideline provided in this article are pretty common to every design, its the job of the engineer to apply industry-specific guidelines also to achieve the best possible result. Some guidelines based on experience can be invaluable to the board designer. However, using the guideline without understanding the physics behind it will result in wasted effort and non-functional boards. Understanding the basic physics behind each and every guideline applied is very important. Identifying potential sources of noise, antennas and coupling paths with each design is important. We have already published a detailed checklist for PCB, it will be wise to make use of it and if required add more checkpoints. It is strongly advisable to get the design reviewed by a third person with enough experience in the field before reaching out to the manufacturing process.
- 6 Steps of verification for error-free schematic
- 100 Point checklist for schematic design
- Selecting a PCB stack-up for EMC compliance
- Strategy for component placement
- Decoupling – Path to power integrity
- 15 PCB Layout guidelines to achieve EMC requirements
- 4 steps to review the PCB layout
- Checklist for error-free optimized PCB layout
- Engineered to doom – Red flags for PCB design
- Board bring up: Giving life to the design